Use this semiconductor calculation for first-order device, material, fabrication, interconnect, packaging, or reliability estimates when every coefficient and unit convention is known.

Pitch (nm)

Required number in nm. Lithographic pitch of the patterned layer.

Overlay fraction of pitch

Required number. Allowed overlay error as a fraction of the pitch, between zero and one.

The cited overview of Photolithography supplies background for the terminology and domain context used by this tool.^[1]

Compute the overlay accuracy budget as a fraction of the lithographic pitch. Inputs are interpreted exactly in the displayed units and the calculation returns the following fields without presentation rounding.

Overlay budget (nm)

Returned number in nm. Total overlay budget for the layer.

• Material composition, geometry, process history, temperature, electric field, bias, interfaces, parasitics, and fitted parameter ranges can invalidate a compact semiconductor model.
• Pitch must be at least 5e-324.
• Overlay fraction of pitch must be at least 0.
• Overlay fraction of pitch must be no greater than 1.
• Use finite inputs in the displayed units, preserve source measurements and assumptions, and independently verify consequential decisions.

Compare the estimate with measured process data, current device documentation, and a higher-fidelity circuit, field, thermal, quantum, or TCAD model when the decision requires it.

• Depth of Focus Calculator

  Compute the lithographic depth of focus from the k2 factor, exposure wavelength, and numerical aperture.

• Rayleigh Resolution Calculator

  Compute the Rayleigh lithographic resolution from the k1 factor, exposure wavelength, and numerical aperture.

• TSV Keep-Out Zone Calculator

  Compute the placement keep-out zone around a through-silicon via from its pitch and a keep-out ratio. Keep-out = pitch × ratio.