Description
Map CPOL zero to a rising first edge and one to falling.
SPI clock polarity determines idle level and the first transition; clock phase determines which edge samples data. Word and idle budgets describe separate parts of the transfer.
Map CPOL zero to a rising first edge and one to falling.
When to use this tool
Use SPI Cpha First Edge Action Token when you need an explicit SPI mode or clock-budget component.
How to use the tool and how it works
- Enter cpha, cpol. Use the units and conventions below.
- Run the tool. Correct any format, range, or cross-field input error before interpreting the output.
- Read firstEdge, action, idleLevel. Use the output convention below.
Map CPOL zero to a rising first edge and one to falling. Map CPHA zero to first-edge sample and one to first-edge shift; return idleLevel.1
| Input field | Meaning and units | Accepted input |
|---|---|---|
| cpha | Cpha | Required. Safe integer; minimum 0; maximum 1. |
| cpol | Cpol | Required. Safe integer; minimum 0; maximum 1. |
| Output field | Interpretation | Returned shape |
|---|---|---|
| firstEdge | First Edge | Required. Text; maximum UTF-16 length 8192. |
| action | Action | Required. Text; maximum UTF-16 length 8192. |
| idleLevel | Idle Level | Required. Safe integer. |
{
"input": {
"cpha": 0,
"cpol": 0
},
"output": {
"firstEdge": "rising",
"action": "sample",
"idleLevel": 0
}
}Limitations and assumptions
- Only nominal edge roles are labeled; setup, hold, and actual controller timing are not evaluated.
- Inputs must satisfy both the field types and the cross-field conditions above. Invalid input causes an error; a successful false flag or documented placeholder is a different result.
- Numeric calculations use binary floating point unless exact decimal-integer arithmetic is explicitly stated. No hidden measurement tolerance or decimal rounding is added; nonfinite or out-of-contract results are rejected. Numeric signed-zero results are exported as zero.
Alternative or Complementary methods
Compare both devices' timing requirements and verify the actual chip-select and clock waveform.
References
Similar or alternative tools
- Microcontroller: SPI Clock Edge Number Label
Return the idle level, leading edge, sampling and shifting edge numbers, and mode = 2 × clockPolarity + clockPhase.
- SPI Idle Level Sample Sign
Use CPOL to choose the leading edge and CPHA to select the leading or trailing sampling edge.