Description
Return the idle level, leading edge, sampling and shifting edge numbers, and mode = 2 × clockPolarity + clockPhase.
SPI clock polarity determines idle level and the first transition; clock phase determines which edge samples data. Word and idle budgets describe separate parts of the transfer.
Return the idle level, leading edge, sampling and shifting edge numbers, and mode = 2 × clockPolarity + clockPhase.
When to use this tool
Use Microcontroller: SPI Clock Edge Number Label when you need an explicit SPI mode or clock-budget component.
How to use the tool and how it works
- Enter clockPolarity, clockPhase. Use the units and conventions below.
- Run the tool. Correct any format, range, or cross-field input error before interpreting the output.
- Read result. Expand result to inspect the returned fields.
Return the idle level, leading edge, sampling and shifting edge numbers, and mode = 2 × clockPolarity + clockPhase.1
| Input field | Meaning and units | Accepted input |
|---|---|---|
| clockPolarity | Clock Polarity | Required. Safe integer. |
| clockPhase | Clock Phase | Required. Safe integer. |
| Output field | Interpretation | Returned shape |
|---|---|---|
| result | Result | Required. Object. |
| result.idleLevel | Idle Level | Calculated result member: number. |
| result.leadingEdge | Leading Edge | Calculated result member: string. |
| result.sampleEdgeNumber | Sample Edge Number | Calculated result member: number. |
| result.shiftEdgeNumber | Shift Edge Number | Calculated result member: number. |
| result.mode | Mode | Calculated result member: number. |
{
"input": {
"clockPolarity": 0,
"clockPhase": 1
},
"output": {
"result": {
"idleLevel": 0,
"leadingEdge": "rising",
"sampleEdgeNumber": 2,
"shiftEdgeNumber": 1,
"mode": 1
}
}
}Limitations and assumptions
- Both control bits must be zero or one; device compatibility and waveform quality are not inferred.
- Outputs are nested inside result. Inputs must satisfy both the field types and the cross-field conditions above. Invalid input causes an error; a successful false flag or documented placeholder is a different result.
- Numeric calculations use binary floating point unless exact decimal-integer arithmetic is explicitly stated. No hidden measurement tolerance or decimal rounding is added; nonfinite or out-of-contract results are rejected. Numeric signed-zero results are exported as zero.
Alternative or Complementary methods
Compare both devices' timing requirements and verify the actual chip-select and clock waveform.
References
Similar or alternative tools
- SPI Idle Level Sample Sign
Use CPOL to choose the leading edge and CPHA to select the leading or trailing sampling edge.
- SPI Cpha First Edge Action Token
Map CPOL zero to a rising first edge and one to falling.