Use this electronics calculation for a first-pass component, converter, signal, motor, or sensor estimate when the stated operating conditions and units match the device data.

Unit interval (ps)

Required number input.

Required eye width (ps)

Required number input.

Other timing penalty (ps)

Required number input.

Subtract a required open-eye width and other timing penalties from one unit interval to obtain remaining total jitter budget. All inputs are in picoseconds; apply the limits from the relevant USB generation and test specification. The tool evaluates the supplied inputs together and returns the named outputs below; it does not infer omitted operating conditions or change the units shown.^[1]

Jitter Budget ps

The resulting jitter budget ps returned as a number.

• USB overhead and eye or jitter budgets depend on USB generation, encoding, packet type, topology, channel loss, equalization, reference clock, compliance pattern, and protocol scheduling. Payload throughput is lower than raw signaling rate.
• Use finite inputs in the displayed units and preserve more precision than the final presentation requires. Independently verify safety-critical, financial, compliance, or production decisions.

Check the result against the current datasheet and worst-case operating corners, then verify the circuit or measurement with simulation and bench testing where failure matters.

• Eye Width Estimate

  Find the horizontal eye opening between the latest left crossing and earliest right crossing in one unit interval.

• FPGA Clock Jitter Allowance

  Calculate remaining setup-time budget for combined clock jitter after clock period, clock-to-output, combinational path delay, setup time, and skew. Use worst-case values in the same time unit.

• Jitter Budget Allocation

  Find the remaining independent random-jitter RMS allowance by subtracting used RMS jitter in quadrature from a total RMS budget.