Use this semiconductor calculation for first-order device, material, fabrication, interconnect, packaging, or reliability estimates when every coefficient and unit convention is known.

Total capacitance (fF)

Required number in fF. Total capacitance of the island to its surroundings. Must be greater than 0 fF.

The cited overview of Quantum tunnelling supplies background for the terminology and domain context used by this tool.^[1]

Compute the Coulomb-blockade voltage e over twice the total capacitance of an island. Formula: Vb [mV] = 80.108832 / C [fF] (since e/(2·C) with e=1.602176634e-19 C, 1 fF=1e-15 F, converted to mV). Input: C > 0 fF. Output: Vb > 0 mV. Assumes an isolated metallic island at zero temperature and that C is the total capacitance to all surroundings. Inputs are interpreted exactly in the displayed units and the calculation returns the following fields without presentation rounding.

Blockade voltage (mV)

Returned number in mV. Blockade voltage threshold for single-electron charging. At least 0 mV.

• Material composition, geometry, process history, temperature, electric field, bias, interfaces, parasitics, and fitted parameter ranges can invalidate a compact semiconductor model.
• Total capacitance must be at least 5e-324.
• Use finite inputs in the displayed units, preserve source measurements and assumptions, and independently verify consequential decisions.

Compare the estimate with measured process data, current device documentation, and a higher-fidelity circuit, field, thermal, quantum, or TCAD model when the decision requires it.

• Diffusion Capacitance Calculator

  Compute the diffusion capacitance of a forward-biased diode from stored-charge lifetime and current. Formula: Cdiff [nF] = 1e9 · (τ [ns]·1e-9 · I [mA]·1e-3) / (n · Vt [V]), where Vt = k·T/q (k=1.380649e-23 J/K, q=1.602176634e-19 C). Equivalent: Cdiff [F] = τ·I/(n·Vt). Inputs: I ≥ 0 mA, τ > 0 ns, n ≥ 1 (default 1), T > 0 K (default 300 K). Output: Cdiff ≥ 0 nF. Assumes low-level injection, negligible depletion capacitance, and quasi-neutral stored charge τ·I.

• Diode Ideality Factor Calculator

  Extract the diode ideality factor n from two forward-bias points on the exponential Shockley relation. Formula: n = (V2 - V1) / (Vt·ln(I2/I1)), where thermal voltage Vt = k·T/q (k=1.380649e-23 J/K, q=1.602176634e-19 C). Inputs: I1>0 mA, I2>0 mA and I1≠I2, V1 and V2 finite V, T>0 K (default 300 K). Output: n>0 (physical diode typically 1 ≤ n ≤ 2; n=1 ideal diffusion, n≈2 recombination/generation; n outside 1-2 indicates series resistance, high injection, or measurement error). Assumes forward exponential region, negligible series resistance, and constant temperature.

• DRAM Retention Time Calculator

  Estimate DRAM retention time from cell capacitance, allowable refresh voltage drop, and leakage current. Formula: t_ret [s] = (C [fF]·1e-15·ΔV [V])/(I_leak [fA]·1e-15) = C·ΔV/I_leak, derived from charge Q=C·ΔV leaking at rate I_leak. Inputs: C>0 fF, ΔV>0 V, I_leak>0 fA. Output: t_ret>0 s. Assumes constant leakage, no refresh overhead, and that the cell holds charge C·V until droop ΔV.