DRAM Retention Time Calculator
Estimate DRAM retention time from cell capacitance, allowable refresh voltage drop, and leakage current. Formula: t_ret [s] = (C [fF]·1e-15·ΔV [V])/(I_leak [fA]·1e-15) = C·ΔV/I_leak, derived from charge Q=C·ΔV leaking at rate I_leak. Inputs: C>0 fF, ΔV>0 V, I_leak>0 fA. Output: t_ret>0 s. Assumes constant leakage, no refresh overhead, and that the cell holds charge C·V until droop ΔV.
Description
Estimate DRAM cell retention time from capacitance, allowable voltage droop, and constant leakage current.
Estimate DRAM retention time from cell capacitance, allowable refresh voltage drop, and leakage current. Formula: t_ret [s] = (C [fF]·1e-15·ΔV [V])/(I_leak [fA]·1e-15) = C·ΔV/I_leak, derived from charge Q=C·ΔV leaking at rate I_leak. Inputs: C>0 fF, ΔV>0 V, I_leak>0 fA. Output: t_ret>0 s. Assumes constant leakage, no refresh overhead, and that the cell holds charge C·V until droop ΔV.
When to use DRAM Retention Time Calculator
- Estimate DRAM cell retention time from capacitance, allowable voltage droop, and constant leakage current.
- Compare fabrication or device scenarios while holding coefficients and unit conventions constant.
- Check a hand calculation before moving to a higher-fidelity process, circuit, or TCAD model.
How the calculation works
Because femtofarads and femtoamperes share the same 10⁻15 factor, their prefixes cancel and the direct numeric ratio is in seconds.
tret = C·ΔV/Ileak Interpreting the result
Because femtofarads and femtoamperes share the same 10⁻15 factor, their prefixes cancel and the direct numeric ratio is in seconds.
Assumptions and limitations
- Leakage is assumed constant; real retention varies strongly with temperature, stored state, access transistor, trap history, and variable retention-time effects.
- Use parameters measured for the same material, geometry, temperature, and operating regime whenever the result informs engineering work.