Depletion Width Abrupt Junction Calculator
Compute the total depletion width of an abrupt pn junction from built-in and applied reverse bias. Assumes silicon permittivity 11.7·ε0.
Description
Compute the total depletion width of an abrupt pn junction from built-in and applied reverse bias. Assumes silicon permittivity 11.7·ε0.
Depletion Width Abrupt Junction Calculator is a focused tool for the following task. Compute the total depletion width of an abrupt pn junction from built-in and applied reverse bias. Assumes silicon permittivity 11.7·ε0. It reports Depletion width from the values you provide rather than inventing measurements, coefficients, or professional judgment that are not part of the input.
When to use Depletion Width Abrupt Junction
Use this semiconductor calculation for first-order device, material, fabrication, interconnect, packaging, or reliability estimates when every coefficient and unit convention is known.
- NA (cm^-3)
- Required number in cm^-3. Acceptor concentration on the p side. Must be greater than 0 cm^-3.
- ND (cm^-3)
- Required number in cm^-3. Donor concentration on the n side. Must be greater than 0 cm^-3.
- Built-in voltage (V)
- Optional number in V. Built-in potential of the junction. Must be at least 0 V.
- Reverse bias (V)
- Optional number in V. Applied reverse bias. Must be at least 0 V; total voltage must be >=0.
The cited overview of P–n junction supplies background for the terminology and domain context used by this tool.1
How Depletion Width Abrupt Junction works
Compute the total depletion width of an abrupt pn junction from built-in and applied reverse bias. Assumes silicon permittivity 11.7·ε0. Inputs are interpreted exactly in the displayed units and the calculation returns the following fields without presentation rounding.
- Depletion width (µm)
- Returned number in µm. Total depletion region width.
Limitations and assumptions
- Material composition, geometry, process history, temperature, electric field, bias, interfaces, parasitics, and fitted parameter ranges can invalidate a compact semiconductor model.
- NA must be at least 5e-324.
- ND must be at least 5e-324.
- Built-in voltage must be at least 0.
- Reverse bias must be at least 0.
- Use finite inputs in the displayed units, preserve source measurements and assumptions, and independently verify consequential decisions.
Alternative or Complementary approaches
Compare the estimate with measured process data, current device documentation, and a higher-fidelity circuit, field, thermal, quantum, or TCAD model when the decision requires it.
References
-
P–n junction — Wikipedia contributors
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