Use this electronics calculation for a first-pass component, converter, signal, motor, or sensor estimate when the stated operating conditions and units match the device data.

Reference frequency (Hz)

Frequency of the reference oscillator.

Loop divider

Feedback divider ratio N.

Bandwidth divisor

Documented divisor applied to the comparison frequency to arrive at the usable loop bandwidth.

Compute the phase-detector comparison frequency that sets the PLL loop bandwidth from the reference frequency, loop divider, and a documented reference divider (default ten). The tool evaluates the supplied inputs together and returns the named outputs below; it does not infer omitted operating conditions or change the units shown.^[1]

Loop bandwidth (Hz)

Estimated closed-loop bandwidth.

• PLL bandwidth, margin, lock time, output frequency, spur, and integrated-jitter estimates depend on loop order, charge pump, divider values, oscillator gain, reference noise, nonlinear acquisition, and the exact phase-noise integration limits. Simplified linear models primarily describe locked small-signal behavior.
• Use finite inputs in the displayed units and preserve more precision than the final presentation requires. Independently verify safety-critical, financial, compliance, or production decisions.

Check the result against the current datasheet and worst-case operating corners, then verify the circuit or measurement with simulation and bench testing where failure matters.

• PLL Lock Time

  Estimate the settling time of a phase-locked loop using the documented rule that lock takes roughly four time constants of the natural frequency in radians per second (4 divided by two pi times the loop bandwidth in Hz).

• PLL Output Frequency

  Compute the output frequency of a phase-locked loop from the reference frequency and divider ratios.

• Frequency Synthesizer Step Size

  Frequency increment for an integer-N PLL synthesizer after reference divider R.